1. Field of the Invention
The present invention relates to methods of rewriting a flash memory, more particularly, to methods of rewriting a flash memory with floating gates.
2. Description of Related Art
The conventional flash memories with floating gates are roughly classified, based on the structure of cell array, into two types, the NAND type and the NOR type. Now the NOR type is prevailing due to the greater reading speed thereof.
FIG. 3 shows a diagram illustrating an equivalent circuit of a cell array of an NOR-type flash memory. In FIG. 3, each of the reference characters M11, M12, M1n, M21 and Mn1 denotes a memory cell which has a floating gate. Each of the memory cells M11, M12 and M1n is connected to a word line WL1 through a control gate. The memory cell M21 is connected to a word line WL2 through a control gate, and the memory cell Mn1 is connected to a word line WLn through a control gate. Each of the memory cells M11, M12, M1n, M21 and Mn1 is also connected to a common source line SL through a source. Each of the memory cells M11, M21, Mn1 is connected to a bit line BL1 through a drain, the memory cell M12 is connected to a bit line BL2 through a drain and the memory cell M1n is connected to a bit line BLn through a drain.
The cell array constructed as described above is generally formed in a well of a desired conductivity type on a semiconductor substrate. Peripheral circuits with CMOS and the like may also be formed in a plurality of wells each having any desired conductivity type on the substrate.
There are four main methods for rewriting the above mentioned NOR-type flash memories by releasing electrons out of the floating gate to the source:
The table 1 shows an example of a first method.
TABLE 1 ______________________________________ Substrate Source Drain Control Gate ______________________________________ Writing 0 V 0 V +5 V +12 V Erasing 0 V +12 V open 0 V Reading 0 V 0 V +2 V +5 V ______________________________________
According to this method, the writing is operated by injection into the floating gate of hot electrons which are generated in a channel by applying 0 V to the substrate and the source, a relatively high positive voltage (+5 V) to the drain, and a high voltage (+12 V) to the control gate. The erasing is operated by release of electrons from the floating gate to the source with FN (Fowler-Nordheim) current caused by applying 0 V to the substrate and the control gate, making the drain open and applying a high voltage (+12 V) to the source. In reading, the written or unwritten state of a memory cell is discriminated by the magnitude of the current that flows through the memory cell caused by applying 0 V to the substrate and the source, a low positive voltage (+2 V) to the drain and a relatively high voltage (+5 V) to the control gate.
The above described rewriting method has disadvantage in the cell size reduction because it is necessary to secure the sufficient junction breakdown voltage of the source due to the high voltage applied to the source when the memory cell is erased and therefore the junction of the source should be deep and the channel needs to be sufficiently long.
A second method is a method wherein lower voltage is applied to the source when the memory cell is erased. The table 2 shows an example thereof.
TABLE 2 ______________________________________ Substrate Source Drain Control Gate ______________________________________ Writing 0 V 0 V +5 V +12 V Erasing 0 V +5 V open -12 V Reading 0 V 0 V +2 V +5 V ______________________________________
The method is different from the first method in that the leakage current passing from the source to the substrate is reduced (up to 1/10) by applying a negative voltage (-12 V) to the control gate in erasing. The operations for writing and reading are the same as in the first method. In addition, in the second method, the potential difference between the source and the control gate is larger than that in the first method so that the same or larger potential difference can be secured between the floating gate and the source compared with the potential difference between the floating gate and the source in the first method.
In the above described second method, a flash memory shown in FIG. 4 is essential because the negative voltage is applied in erasing. That is, an NMOS 28 included in a peripheral circuit Ca which serves to supply the voltage to a memory cell Ma must be formed in a P-well 23 which is electrically separated from a P-type substrate 20 by a deep N-well 24 in order that a source and drain region 29 where N.sup.+ is diffused may be reversely biased to the P-well 23; and when the negative voltage is applied, the maximum negative voltage must be applied to the P-well 23 via a terminal 27, although the P-type substrate 20 should be biased at 0 V. In the flash memory shown in FIG. 4, the memory cell Ma is formed in a P-well 21 disposed in the surface layer of the P-type substrate 20. To the P-type substrate 20 a desired voltage is applied via a terminal 25. Additionally, since a CMOS is also included in the peripheral circuit Ca, a plurality of wells (e.g. an N-well 22) besides the above P-well are also formed, to each of which a desired voltage is applied via a terminal (for example to the N-well 22 the power supply voltage is applied via a terminal 26).
A third method is shown in the table 3.
TABLE 3 ______________________________________ Substrate Source Drain Control Gate ______________________________________ Writing 0 V 0 V +5 V +12 V Erasing 0 V 0 V open +18 V Reading 0 V 0 V +2 V +5 V ______________________________________
The third method is different from the first and second methods in that the written and erased states of a memory cell in the third method are opposite to those in the first and second methods: In the first and second methods, the memory cell is charged with electrons when it is written and is discharged of electrons when it is erased; in the third method, on the contrary, the memory cell is discharged of electrons when it is written and is charged with electrons when it is erased. In the third method, the writing is operated by release of electrons from the floating gate with FN (Fowler-Nordheim) current caused by applying 0 V to the P-type substrate, making the source open, applying a high negative voltage (-12 V) to the control gate and a relatively high positive voltage (+5 V) to the drain. The erasing is operated by injection of electrons with FN current into the floating gate from a channel in the substrate which is induced by applying 0 V to the substrate and the source, making the drain open and applying a high positive voltage (+18 V) to the control gate. The third method has the advantage of saving the electric power employed because the third method, utilizing the FN current in writing, needs smaller current (up to 1/10.sup.5) in writing than the first and second methods. In reading, the third method is the same as the first and second methods.
The above described third method also needs a flash memory as shown in FIG. 4 since the high negative voltage is applied to the control gate in writing as in the second method.
Further as an improved third method, the fourth method shown in the table 4 is known.
TABLE 4 ______________________________________ P- Control Substrate well Source Drain Gate ______________________________________ Writing 0 V 0 V open +5 V -12 V Erasing 0 V -8 V -8 V open +10 V Reading 0 V 0 V 0 V +2 V +5 V ______________________________________
As shown in FIG. 5, a P-well 34 in a peripheral circuit Cb, formed in a deep N-well 35, is electrically separated from a P-type substrate 30, a terminal 38 serving to apply a desired voltage to the P-well. And at the same time a P-type region (P-well 32) which provides a channel for a memory cell Mb is also electrically separated by a deep N-well 31, a terminal 36 serving to apply a relatively high negative voltage (-8 V) to the P-well 32 and the source in erasing. Thus, the positive voltage applied to the control gate in erasing is reduced. Additionally, since a CMOS is formed in the peripheral circuit Cb of the flash memory shown in FIG. 5, a plurality of wells (e.g. an N-well 33) besides the above P-well are formed, to each of which a desired voltage is applied via a terminal (for example to the N-well 33 the power supply voltage is applied via a terminal 37).
Further, a fifth method is shown in the table 5 which differs from the first and second methods in the erasing mode.
TABLE 5 ______________________________________ P- Control Substrate well Source Drain Gate ______________________________________ Writing 0 V 0 V 0 V +5 V +12 V Erasing 0 V 5 V open open -13 V Reading 0 V 0 V 0 V +1 V +5 V ______________________________________
The method also needs a flash memory as shown in FIG. 5. The erasing is operated by releasing electrons out of the floating gate to the P-well by providing a large potential difference between the control gate and the P-well. This method is called channel erasing (or substrate erasing) since the P-well 32 corresponds to the channel of the memory cell Mb.
The erasing method is not suitable for the reduction of the employed voltage because the method generally has the disadvantage of requiring high voltages. The reason will be explained in the following paragraphs by comparing the method with the second one:
The erasing state is determined by the potential difference between the floating gate and the source in the second method, while in the fifth method the erasing is introduced by the potential difference between the floating gate and the P-well. The potential of the floating gate is determined by the coupling capacitances with the control gate, the source, the drain and the channel (the P-well) and expressed in the following formula: EQU Vfg=Ccg.times.Vcg+Cs.times.Vs+Cd.times.Vd+Cpw.times.Vpw
wherein the reference characters Vfg, Vcg, Vs, Vd, Vpw, Ccg, Cs, Cd and Cpw are the potential of the floating gate, the potential of the control gate, the potential of the source, the potential of the drain, the potential of the P-well, the coupling capacitance ratio of the floating gate to the control gate, the coupling capacitance ratio of the floating gate to the source, the coupling capacitance ratio of the floating gate to the drain and the coupling capacitance ratio of the floating gate to the P-well respectively.
In general, the coupling capacitance ratio Ccg of the floating gate to the control gate is about 0.6, the coupling capacitance ratio Cs of the floating gate to the source is about 0.05, the coupling capacitance ratio Cd of the floating gate to the drain is about 0.05 and the coupling capacitance ratio Cpw of the floating gate to the P-well is about 0.3.
In the fifth method, the source and drain are open respectively, in erasing and the voltage of the source and drain are determined respectively, by the coupling capacitances with the control gate (via the floating gate) and the P-well, and is almost equal to the voltage of the P-well since the coupling capacitance with the P-well is dominantly large. Therefore, by calculating the voltages given in the table 5, about -5.8 V is obtained for the potential Vfg of the floating gate in erasing, the potential difference between the floating gate and the P-well being about 10.8 V.
Whereas in the second method, supposing that Vcg is -10 V and Vs is 5 V in erasing, 5.75 V is obtained by calculation for the potential Vfg of the floating gate, the potential difference between the floating gate and the source being 10.75 V.
The erasing state in the fifth method at Vcg=-13 V and Vpw=5 V is almost equivalent to the erasing state in the second method at Vcg=-10 V and Vs=5 V, and it is recognized that the second method is more suitable for the reduction of the employed voltage than the fifth method.
As the fine pattern fabrication technology has been developing recently, there is a growing tendency to reduce cell sizes, even a transistor whose gate length is around 0.35 .mu.m being applicable when the applied voltage is low (up to 3 V).
Meanwhile, in the case of the flash memory as described above, there has been a problem with chip size reduction: Since the memory cell needs to be supplied with high voltages, even to an MOS transistor used in a peripheral circuit such as a decoder a high voltage is applied. Accordingly, the gate oxide films of the MOS transistors must be formed to have a thickness of around 200 angstrom. Thus the transistors for the peripheral circuits need to be formed such that the gate lengths thereof are at least around 1 .mu.m.
In order to reduce the area of the peripheral circuits, it is essential to reduce the voltages to be applied in writing and erasing. The reduction of the voltages can be partly realized by employing thinner film for the tunnel oxide film (the insulator film between the substrate and the floating gate) and for the ONO film (the insulator film between the floating gate and the control gate) in a memory cell. However, there is a possibility that the thinner films for the tunnel film and the ONO film will cause a decline in the reliability of the memory cell. There has been a limit, therefore, to the reduction of the voltage to be applied by using thinner film.
It will be hereafter explained the magnitude of voltage to be applied to the peripheral circuits, taking the second method for example, which is particularly designed to reduce the applied voltage.
In a peripheral circuit which serves to supply the drain with voltage, OV is applied to the P-type substrate and the maximum positive voltage (+5 V) in this the peripheral circuit is applied to the N-well in writing. Accordingly, to the transistors of the peripheral circuit 5 V is applied at maximum. In a peripheral circuit which supplies the control gate voltage, on the other hand, 0 V is applied to the P-type substrate and the maximum positive voltage (+12 V) that the peripheral circuit supplies is applied to the N-well in writing. Accordingly, to the transistors of the peripheral circuit 12 V is applied at maximum. Similarly, in erasing, 5 V is applied at maximum to a peripheral circuit which supplies the source voltage (+5 V). Since the peripheral circuit which supplies the control gate voltage operates not only in erasing but also in writing and reading, a voltage of at least Vcc needs to be applied to the N-well. Therefore to the transistors of the peripheral circuits a voltage of 12+Vcc is applied.
For the above described reasons, in order to reduce the employed voltage in the second method, it is necessary to reduce the voltage, that is, the absolute value of the voltage, applied to the control gate in erasing.
In the fourth method, the writing being operated in the same way as the erasing in the second method except that the states of the source and drain are switched each other, 12+Vcc at maximum is applied to the transistors of the peripheral circuit supplying voltage for the control gate. In erasing, 10 V at maximum is applied to the peripheral circuit supplying voltage to the control gate and 8+Vcc (3 to 5 V) at maximum is applied to the peripheral circuit supplying voltage for the source, according to the table 4.
Therefore, in order to reduce the employed voltage in the fourth method, it is necessary to reduce the voltage applied to the control gate in writing.